This invention relates to integrated circuits with memory cells, and more particularly, to circuitry for enhancing the stability of memory cell arrays.
Memory arrays are used in integrated circuits such as integrated circuit memories and programmable logic devices.
Programmable logic devices are a type of integrated circuit that can be programmed by a user to implement a desired custom logic function. In a typical scenario, a logic designer uses computer-aided design (CAD) tools to design a custom logic circuit. These tools help the designer to implement the custom logic circuit using the resources available on a given programmable logic device. When the design process is complete, the CAD tools generate configuration data files. The configuration data is loaded into programmable logic devices to configure them to perform the desired custom logic function.
Programmable logic devices contain programmable memory elements such as random-access-memory cells into which configuration data is loaded during device programming. Programmable logic devices also contain arrays of random-access-memory cells that are used for handling data that is being processed by circuitry on the devices during normal device operation.
Memory arrays are often used to store critical data. With conventional techniques, memory cell stability is ensured by adjusting transistor sizes. Redundant resources may also be provided so that defects can be repaired by switching redundant circuitry into use. Although these approaches are sometimes satisfactory, they can lead to undesirable overhead in an integrated circuit design.
It would therefore be desirable to be able to provide improved techniques to improve memory cell stability.